During the electronic circuit design process, to design an integrated circuit (IC), a circuit designer generates a register-transfer level (RTL) design. An RTL design is a design abstraction that models a circuit in terms of the flow of signals (e.g., data) between hardware registers, and the logical operations performed on those signals. Hardware description languages (HDLs), such as Verilog, SystemVerilog, and VHDL, are used to generate the RTL abstraction. The RTL abstraction creates a high-level representation of the circuit, from which lower-level representations and actual circuit wiring can be derived. The RTL design is the golden design. The derived lower-level representation is the derived design.
The derived design is generated by synthesis software tools or by manual implementation from the golden RTL design. After the derived design is generated from the RTL design, the circuit designer uses verification software to verify that the derived design is logically equivalent (e.g., EQ) to the golden RTL design, which is the circuit design originally intended by the circuit designer. There are two main categories of design mismatches: the design intent mismatches and the simulation and/or synthesis mismatches. The design intent mismatches can happen when the designer misunderstands the RTL language semantics. Currently, verification software is not able to detect design intent mismatches that occur between the circuit designer's intent and RTL language semantic interpretations of the golden RTL design. As such, when a mismatch between the circuit designer's intent and language interpretations is present, the verification software may return a result of equivalence (EQ) between the derived design and the golden RTL design, which can be misleading to the circuit designer. The simulation and/or synthesis mismatches can happen when the golden RTL code is interpreted differently by the simulation tools and by the synthesis tools because the tools take different assumptions and constraints. This is due to the fact that the software has a different interpretation for the RTL design code and/or due to extra constraints being applied to the software. Currently, the simulation and/or synthesis mismatches are hard to detect by simulation tools because simulation tools have well-known issues of low verification coverage. The simulation and/or synthesis mismatches can be undetected by the equivalence check because it shares the same assumptions and constraints used by the synthesis tools. The present disclosure addresses this design mismatch problem by providing an improved approach for design checking golden RTL designs.